In the field of semiconductor manufacturing, physical descriptions of microdevice layouts are generally represented using data formats such as GDSII. In this representation, individual circuit elements are represented by polygons, which are typically described as a sequence of vertices. The circuit elements placed in the various physical layers in the device are represented by data layers in the description. Related groups of device elements on various layers can be combined in a description of a subset of the layout, often called a cell. In turn, cells can contain other, smaller cells, or be contained in larger cells. The organization of cells (each of which can contain data for multiple layers) into a tree structure is often called the hierarchy of the device.
It is clear that a hierarchical representation can represent an entire layout with greater compactness than a representation with no hierarchy, also called a flat representation. Products that import layout files for verification such as Calibre® from Mentor Graphics Corporation, the assignee of the present invention, strive to retain as much of the original hierarchy as possible, and can in some cases reorganize the hierarchy or create additional levels of hierarchy for additional data compactness. An efficient hierarchical database can significantly reduce the size of the file required to describe the microdevice layout.
In many instances, a circuit as designed on a computer will not perform as anticipated due to capacitances that occur between the physical microelectronic elements that comprise the circuit as well as the small but measurable resistance of these elements. To ensure that the circuit will operate properly, it is necessary to model these capacitances and resistances and to make appropriate changes to the layout prior to fabricating the device. Parasitic plate capacitances are created due to the area of a circuit element and its distance to the circuit's substrate. Parasitic fringe capacitances are those capacitances between the vertical sides of a circuit element and a substrate. Capacitances occurring between circuit elements on the same layer of the circuit are referred to as “near body” capacitances and capacitances occurring between circuit elements on different layers of the circuit are called crossover capacitances.
A conventional method of modeling these capacitors is to flatten a hierarchical database, i.e. to analyze a database that includes a complete description of every circuit element to be created in the circuit. However, such an approach can create extremely large files and therefore require a large amount of memory and computer time to analyze. In addition, because many elements of a circuit are repeated throughout a layout, computing the capacitances and resistances of the circuit elements often means that such calculations must be repeated regardless of the fact that calculations for the same element at a different location in the layout have already been performed.
Given these problems, there is a need for a system and method that reduces the time required to model the capacitances and resistance of circuit elements in an integrated circuit design.